1. Field of the Invention
The present invention relates to a variable gain amplifying circuit for processing an analog signal in a MOS type semiconductor integrated circuit.
2. Description of the Related Art
In recent years, as digital units have been widely used and digital signal processing technologies have been advanced, CMOS type integrated circuits suitable for processing digital signals have shared most part of integrated circuits in the semiconductor market.
However, since video signals and audio signals are inputted and outputted as analog signals, they can be easily processed as analog signals. When such signals are processed as digital signals, analog circuits are required for an A/D converter, a D/A converter, filters, an oscillator for a clock signal, and so forth.
A bipolar type integrated circuit is suitable for an analog circuit. A CMOS type integrated circuit is not suitable for an analog circuit except for part of circuits such as an analog switch and a sample hold circuit. However, the fabrication process for a bipolar type integrated circuit and a Bi-CMOS type integrated circuit is relatively expensive. In addition, it is desired to structure one chip CMOS type integrated circuit that has both a digital circuit and an analog circuit. Thus, CMOS type integrated circuits that process analog signals have been intensively developed.
A circuit that is frequently used and that largely affects the performance of a final product is a "variable gain amplifier". As a bipolar type integrated circuit, a hybrid transistor circuit named "gain cell" has been used. When a variable gain amplifier is structured with such a "gain cell", a circuit that has a gain proportional to the ratio of two bias currents can be easily accomplished.
When a variable gain amplifier is structured with a CMOS type integrated circuit, if the bipolar type integrated circuit is substituted with a CMOS type integrated circuit or a modification circuit, a large secondary distortion always takes place. FIG. 9 shows the structure of a variable gain differential amplifier composed of a CMOS type integrated circuit that is disclosed in Japanese Patent Laid-Open Application No. 8-298416. Next, with reference to the CMOS type variable gain differential amplifier, problems of the conventional circuit will be described.
The circuit shown in FIG. 9 comprises a first differential transistor circuit and a second differential transistor circuit. The first differential transistor circuit is composed of MOS transistors M1 and M2 and a current source I1. Likewise, the second differential transistor circuit is composed of MOS transistors M3 and M4 and a current source I2. In each of the first differential transistor circuit and the second differential transistor circuit, a pair of source coupled transistors are biased with a current source. Next, the first differential transistor circuit composed of the MOS transistors M1 and M2 and the current source I1 will be described. However, for simplicity, it is assumed that input signals are fully-differential signals, both the transistors operate in a saturation region (pinch-off region) and that a short channel effect is not considered.
At this point, the characteristic of each MOS transistor can be represented with a principal parameter k and a threshold voltage Vth as follows. EQU I=(k/2)(VGS-Vth).sup.2
where k is a constant represented by .mu.CoxW/L (W represents the gate width; L represents the gate length; Cox represents the gate capacitance; .mu. represents the carrier mobility of channel). With the formula, the operations of the MOS transistors M1 and M2 are expressed as follows. EQU M1:I11=(k/2)(VGS1-Vth).sup.2 (1) EQU M2:I12=(k/2)(VGS2-Vth).sup.2 (2)
When Eq. (1)-Eq. (2) is calculated, the following result is obtained. ##EQU1## where VGS1 represents the gate-source voltage of the MOS transistor M1; VGS2 represents the gate-source voltage of the MOS transistor M2; and Vin represents the differential input voltage. Since it is assumed that input signals are fully-differential signals, when the mid-point voltage of the input signals is denoted by VB, the input voltages supplied to the input terminals are expressed by VB+Vin/2 and VB-Vin/2.
The source voltage VA of the differential transistor pair is calculated as follows. EQU VGS1=VB+Vin/2-VA EQU VGS2=VB-Vin/2-VA
Thus, assuming that VB-VA-Vth=A, by adding Eq. (1) +Eq. (2), ##EQU2## Substituting the above expressions into Eq. (3), the trans-conductance Gm1 [=(I11-I12)/Vin] can be obtained as follows. ##EQU3## Likewise, the trans-conductance Gm2 [=(I21-I22)/Vin] of the second differential transistor circuit composed of the MOS transistors M3 and M4 and the current source I2 is obtained as follows. ##EQU4## However, it is assumed that the parameter k and the threshold voltage Vth for the MOS transistors M3 and M4 are the same as those for the MOS transistors M1 and M2. Since the output signals with reverse polarities of the two differential transistor circuits are connected, the resultant trans-conductance Gm is obtained by the difference between Eq. (5) and Eq. (6). ##EQU5## As is clear from Eq. (7), the trans-conductance Gm dynamically varies corresponding to an instantaneous amplitude value Vin of the input signals. In other words, the output signals have a distortion. Since the trans-conductance Gm includes a square term of the differential input voltage Vin, the distortion in the output signals is mainly a secondary distortion. With a load that is a linear device such as a resistor or a load that is an MOS transistor with a secondary characteristic, the secondary distortion cannot be canceled. In this case, the distortion of the waveform is very complicated. When a variable gain amplifier is structured with CMOS transistors, a large distortion inevitably takes place and thereby, the quality of the output signal deteriorates.